Elements: Open Infrastructure for Automated Synthesis of AI Models to Hardware

Artificial intelligence (AI) is rapidly transforming science, industry, and national security, yet the infrastructure required to translate modern AI models into efficient hardware remains costly, fragmented, and inaccessible to much of the research and innovation community. This project establishes a shared, open cyberinfrastructure platform that enables automated, interoperable, and reproducible translation of AI models into optimized hardware designs. By providing a community accessible foundation that integrates with existing machine learning and electronic design ecosystems, the project lowers barriers for universities, small businesses, and under-resourced institutions to participate in advanced AI hardware development. The platform supports a broad range of users through open-source software, standardized interfaces, and sustained community engagement, including training materials, course modules, and workshops. The resulting infrastructure is expected to accelerate innovation in areas such as healthcare, environmental monitoring, and edge computing, while strengthening workforce development and promoting inclusive participation. By expanding access to advanced AI chip design capabilities, the project contributes to national prosperity, technological competitiveness, and security. This project develops a unified, open compiler infrastructure that automates the translation of AI models into application-specific integrated circuit (ASIC) and field-programmable gate array (FPGA) hardware, emphasizing interoperability, extensibility, and reproducibility across the full design flow. It introduces new and extended intermediate representations that connect existing machine learning and hardware compiler ecosystems, ensuring that dataflow structure, tensor properties, and execution semantics are preserved continuously from model specification to hardware implementation. These abstractions enable efficient compilation of both dense and sparse workloads, with hardware-aware scheduling and resource management guiding the process. The platform integrates performance and power estimations to provide continuous feedback for design optimization and incorporates verification methods to ensure correctness across software and hardware layers. It supports standardized benchmarking and evaluation across representative AI workloads and enables seamless integration with open electronic design automation tools. The infrastructure is designed for community-driven extension, containerized deployment, and full provenance tracking, allowing researchers and practitioners to build upon, reproduce, and extend the system for diverse applications. This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.